VLSI Design Methods: Formal VLSI Correctness Verification.(VLSI Design Methods: Proceedings of the IFIP WG10.2/WG10.5 internatio
目次
MOS Circuit Level Verification. Efficient Tautology CheckingAlgorithms. Verification of Sequential Machines. FunctionalityExtraction, Comparison and Testing. Register Transfer LevelVerification. Boyer-Moore Theorem Prover Based Verification. HardwareVerification Using HOL.
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